For some decades, understanding and engineering the underlying role of lattice mismatch and dislocations on phonon thermal boundary conductance have been subjects of intensive research activity. As background, a wide-ranging review of knowledge in the field of thermal boundary conductance across solid interfaces, as of its writing, may be found in Hopkins, “Thermal Transport across Solid Interfaces with Nanoscale Imperfections: Effects of Roughness, Disorder, Dislocations, and Bonding on Thermal Boundary Conductance,” ISRN Mechanical Engineering, vol. 2013, 682586 (2013).
Limitations on heat transfer from devices to substrates of high thermal conductivity, however, constitute one of the primary bottlenecks in modern microelectronics engineering, particularly for transformative technologies with high commercial and environmental impact. Heat transfer at the interface between distinct materials may be characterized by the thermal boundary conductance (TBC) across the boundary. TBC is the inverse of thermal boundary resistance.
New technologies based on wide-bandgap semiconductors, such as GaN, GaAs, AlGaN, and ZnO, are poised to be disruptive in smart grid distribution, consumer cell phone networks, electric vehicle power converters, and solid state lighting. However, device performance, efficiency, and life expectancy are limited by heat removal from the semiconductor, as discussed, for example, by Chou, et al., “Degradation of AlGaN/GaN HEMTs under elevated temperature life testing,” Microelectronics Reliability, vol. 44, pp. 1033-38, (2004), which is incorporated herein by reference. For example, a 5° C. increase in temperature above the optimum operating range can decrease the lifetime of a device by half, as discussed by Stoner, et al., “Measurements of the Kapitza conductance between diamond and several metals,” Phys. Rev. Lett., vol. 68, pp. 1563-66, (1992), which is incorporated herein by reference.
Zhou et al., “Relationship of thermal boundary conductance to structure from an analytical model plus molecular dynamics simulations,” Phys. Rev. B, vol. 87, 094303, (2013), incorporated herein by reference, found that a small amount of roughness increased TBC linearly with total interfacial area.
As an alternative to growing one material directly on another, the use of an intermediate thermal interface material (TIM) to bond two surfaces has been explored, for example, by English et al., “Enhancing and tuning phonon transport at vibrationally mismatched solid-solid interfaces,” Phys. Rev. B, vol. 85, pp. 1-14 (2012), incorporated herein by reference. While the intermediate material necessarily adds some thermal resistance, it fills any voids and can alleviate stress during thermal cycling, increasing device lifetimes. In addition, an intermediate layer can improve TBC by serving as a phonon impedance matching layer to bridge two materials with a sharp contrast in vibrational properties.
Carbon nanotube composites have been used as thermal interface materials to achieve TBCs on the order of 0.5 MW/m2K, as described by Cross et al., “A metallization and bonding approach for high-performance carbon nanotube thermal interface materials,” Nanotechnology, vol. 21, 445705 (2010), incorporated herein by reference. Heat transfer limitations arise due to interfacial resistance between the carbon nanotubes. The most successful approach to date has been to use a thin adhesive layer (which might be a soft metal, such as indium, or a thin film of silicon nitride) as described by Cho et al., “Improved thermal interfaces of GaN-Diamond Composite Substrates for HEMT Applications,” IEEE Trans. Components, Packaging and Manufacturing Tech., vol. 3, pp. 79-85 (2013), incorporated herein by reference. A flat interface of GaN bonded to diamond with indium yielded a similar TBC to direct crystal growth, on the order of 15-20 MW/m2K. This method has two additional advantages: it works for a variety of materials combinations and alleviates thermal stresses at the interface. However, these TBC values still represent the critical bottleneck in the heat removal path.
The effect of nanostructured surface features on thermal conductance has been a matter of some contention, with Hopkins et al., “Effects of surface roughness and oxide layer on the thermal boundary conductance at aluminum/silicon interfaces,” 2010 14th International Heat Transfer Conference, pp. 313-19 (2010)) finding a decrease in thermal boundary conductance with surface roughness, while simulations of Tao et al., “Interlaced, Nanostructured Interface with Graphene Buffer Layer Reduces Thermal Boundary Resistance in Nano/microelectronics Systems,” ACS Applied Materials & Interfaces, vol. 9, 989-98 (2016) concluded that nanopillar arrays would improve thermal conductance at interfaces. Tao et al. 2016 reported simulations of various longitudinal configurations of nanopillars, with features of at most tens of Angstroms in height, including various pillar densities and interval ratios. Both of the foregoing publications are included herein by reference.
It would be desirable, therefore, to have techniques for preparing surfaces so as to create an interface that provides thermal conductivity to at least the extent of existing technology and that is amenable to robust manufacture and tolerances. Such methods and apparatus are described below in accordance with embodiments of the present invention.